Computing RET

The Computing RET program hosted by the University of Notre Dame campus is projected to run for 7 weeks (~40-hours per week) from mid-June to early August in 2021.  

The exact dates will be determined in conjunction with the selected cohort in an effort to accommodate any academic schedules impacted by COVID, etc.  Moreover, at the present time it is unclear as to whether or not the site will be run virtually, in-person, or some combination thereof.  However, in the "worst case" the site will be run virtually.  

(Unavailability for short segments in this window will not impact your eligibility, and is something we can work around.)  Benefits include:

  • A stipend of $7000
  • A stipend of $500 throughout the Academic Year to participate in ongoing professional development
  • A stipend of $1500 during the Academic Year for materials to implement developed K-12 curricular module
  • Conference / professional development travel funds
  • 3 non-degree graduate credit hours

(Please contact Michael Niemier with any additional questions;; 574-631-3858)

An overview of possible projects can be found here.

(Please contact for additional information and/or resources.)



The objective of the Computing RET site is to form partnerships between Notre Dame (ND) personnel and high school (HS) teachers and students to help prepare HS students for forthcoming changes to information processing systems.


Most information processing is done via the von Neumann model where we process information by writing software (or code) to describe an algorithm that can solve a problem of interest. Code is compiled (i.e., broken down into a sequence of instructions that a microprocessor understands). Step functionality (i.e., digital instruction encodings) and the digital data for the instructions are stored in a microprocessor’s memory, and are in turn fetched and executed, and the problem’s solution is generated.  For over 30 years, MOS field effect transistors (MOSFETs) have been the mainstay of the now $340B/year semiconductor industry and are used to both process and store information on chip – typically by implementing logic and memory for a von Neumann architecture! Transistor scaling has become limited by physics, cost, and energy concerns. A replacement for the MOSFET has proven to be elusive, and industry and government sponsors are focusing on hardware research that is complemented by application-driven system research to develop new computational models to solve problems of interest.


In this regard, computational models such as machine learning algorithms are already driving research that has been commercialized at companies such as Google, Apple etc., and (ii) industry is working to develop radically different computer architectures to support these models. It is essential that students are prepared for forthcoming changes with respect to how we “process information.”


The site encompasses the hardware and devices used to process information, as well as the software and computational models used to define a solution to a problem of interest.  We focus on systems that (i) are inspired by biology/the brain, (ii) exploit the evolution of a physical system to solve a problem of interest, (iii) can be more easily realized with new information processing technologies, and (iv) can meet the computational needs of emerging applications.

Examples of recent RET research projects and associated classroom modules can be found here. 

Code that shows the functionality of different neural network structures, etc. can be found here

Screenshots 3

(Rajeev Datta, author, instructions can be found here.)